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This course will instruct you in how to configure the PHY layer found in Cyclone® V, Arria® V and Stratix® V embedded transceivers for a custom protocol implementation. You will learn details regarding blocks found in high-speed transceivers as well as the various signals used to interact with those blocks to build high-speed serial interfaces. You will learn how to use the Quartus® II software version 13.0 to configure the transceivers to build a custom PHY and to generate design logic to hook up to your own higher layer functional blocks. For Cyclone IV, Arria II, Stratix IV and HardCopy® IV devices, please see the online training High-Speed Serial Protocol Design with Altera Transceiver Devices .
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