About High Performance Floating Point Processing with FPGAs (ODSP1130)

Learn how high performance floating point can be implemented using FPGAs. This course describes the silicon features and the new design flow that enables floating point to run efficiently on the fixed point architecture of todays FPGAs. The course features an in-depth look at a challenging floating point application (matrix inversion) and how to structure and optimize the application for FPGAs. Performance and throughput figures are given for the matrix inversion example using single precision floating point.