You will learn how to preserve design performance and reduce compilation time by using the incremental compilation feature of the Quartus® II software version 12.1. By the end of this training, you will be able to use LogicLock regions to physically partition (floorplan) your design. You will be able to decide when and when not to use incremental compilation, how best to set up your design hierarchy and source code to support incremental compilation, and how to segment your design into logical design partitions. You will also be able to apply the incremental compilation methodology to both the top-down and team-based design flows.
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